Lightweight implementation of the POSIX threads API for an On-Chip MIPS multiprocessor with VCI interconnect - Archive ouverte HAL Access content directly
Book Sections Year : 2003

Lightweight implementation of the POSIX threads API for an On-Chip MIPS multiprocessor with VCI interconnect

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Abstract

This paper relates our experience in designing from scratch a multi-threaded kernel for a MIPS R3000 on-chip multiprocessor. We briefly present the target architecture build around an interconnect compliant with the Virtual Chip Interconnect (VCI), and the CPU characteristics. Then we focus on the implementation of part of the POSIX 1003.1b and 1003.1c standards. We conclude this case study by simulation results obtained by cycle true simulation of an MJPEG video decoder application on the multiprocessor, using several scheduler organizations and architectural parameters.
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Dates and versions

hal-01534543 , version 1 (07-06-2017)

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Frédéric Pétrot, Pascal Gomez, Denis Hommais. Lightweight implementation of the POSIX threads API for an On-Chip MIPS multiprocessor with VCI interconnect. Embedded Software for SoC, Springer, pp.25-38, 2003, ⟨10.1007/0-306-48709-8_3⟩. ⟨hal-01534543⟩
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