A digital CMOS fully connected neural network with in-circuit learning capability and automatic identification of spurious attractors
Résumé
Describes a completely connected feedback network with 64 binary neurons, using digital CMOS technology. The architecture implements a linear systolic loop, in which each neuron stores locally its own synaptic coefficients, and the potential calculation needs N time steps, each performing N partial weighted sums, to realize the N^2 operations needed. It implements internal learning capabilities, using the Widrow-Hoff rule, which converges towards the pseudo-inverse rule by iteration, thus allowing partial correlation between prototypes, and a higher capacity, compared to the Hebb rule. Also, it implements an internal mechanism for detecting relaxations on spurious states. The average retrieval speed is about 20 mu s, whereas the learning time is approximately 15 to 30 ms for 15 moderately correlated prototypes.
Mots clés
15 to 30 ms
20 mus
64 binary neurons
Eurochip
Hopfield network
N partial weighted sums
N time steps
N/sup 2/ operations
Widrow-Hoff rule
automatic identification of spurious attractors
completely connected feedback network
detecting relaxations on spurious states
digital CMOS technology
digital neural network
fully connected neural network
in-circuit learning capability
internal learning capabilities
learning time
linear systolic loop
own synaptic coefficients
partial correlation between prototypes
pseudo-inverse rule
retrieval speed
spurious states detection
CMOS integrated circuits
VLSI
application specific integrated circuits
digital integrated circuits
neural nets