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Conference papers

3D Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology

Abstract : In this paper, we describe the architecture and implementation of 3D multiprocessor with 3D NoC. The 2 tiers design is based on 16 processors communicating using a 4x2 mesh NoC and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. Due to the limitation when investigating NoC performance using simulation, the purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.
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Submitted on : Wednesday, February 1, 2012 - 2:11:39 PM
Last modification on : Wednesday, May 11, 2022 - 12:06:05 PM
Long-term archiving on: : Wednesday, May 2, 2012 - 2:35:07 AM


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  • HAL Id : hal-00665217, version 1



Mohamad Jabbar, Dominique Houzet, Omar Hammami. 3D Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology. IEEE International 3D System Integration Conference (3DIC), Jan 2012, Osaka, Japan. 3D Applications - p.2-18. ⟨hal-00665217⟩



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