S. Abbaspour, F. Brandner, and M. Schoeberl, A time-predictable stack cache, 16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013), 2013.
DOI : 10.1109/ISORC.2013.6913225

URL : https://hal.archives-ouvertes.fr/hal-01108105

C. Ferdinand, R. Heckmann, and B. Franzen, Static memory and timing analysis of embedded systems code, Proc. of Symposium on Verification and Validation of Software Systems, pp.153-163

C. Ferdinand and R. Wilhelm, Efficient and precise cache behavior prediction for real-time systems, Real-Time Systems, vol.17, issue.2/3, pp.131-181, 1999.
DOI : 10.1023/A:1008186323068

M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge et al., MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538), 2001.
DOI : 10.1109/WWC.2001.990739

A. Jordan, F. Brandner, and M. Schoeberl, Static analysis of worst-case stack cache behavior, Proceedings of the 21st International conference on Real-Time Networks and Systems, RTNS '13, pp.55-64, 2013.
DOI : 10.1145/2516821.2516828

H. S. Lee, M. Smelyanskiy, G. S. Tyson, and C. J. Newburn, Stack value file: custom microarchitecture for the stack, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, pp.5-14, 2001.
DOI : 10.1109/HPCA.2001.903247

S. Park, H. Woo-park, and S. Ha, A Novel Technique to Use Scratch-pad Memory for Stack Management, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1-6, 2007.
DOI : 10.1109/DATE.2007.364509

J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee, PRET DRAM controller, Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '11, pp.99-108, 2011.
DOI : 10.1145/2039370.2039388

S. Abbaspour, A. Jordan, and F. Brandner, Lazy spilling for a time-predictable stack cache: Implementation and analysis, Proc. of the International Workshop on Worst-Case Execution Time Analysis, pp.83-92, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01056216

M. Schoeberl, P. Schleuniger, W. Puffitsch, F. Brandner, C. Probst et al., Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach, OASICS, vol.18, pp.11-21, 2011.
URL : https://hal.archives-ouvertes.fr/inria-00585320

R. T. White, C. A. Healy, D. B. Whalley, F. Mueller, and M. G. Harmon, Timing analysis for data caches and set-associative caches, Proceedings Third IEEE Real-Time Technology and Applications Symposium, pp.192-203, 1997.
DOI : 10.1109/RTTAS.1997.601358

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister et al., Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.7, pp.966-978, 2009.
DOI : 10.1109/TCAD.2009.2013287