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Hierarchical Timed Symbolic Abstract State Machines for precise WCET estimation


The Abstract State Machines have been around for a while, earning their place in the embedded system world. Their formal background makes them suited for proofs, their refinement design method eases the system engineering and their apparent simplicity steepens the end user's learning curve. The numerous extensions that followed have adapted the ASMs to most of the real-time system needs. Our aim is to provide a safe, precise and adaptable worst-case execution time (WCET) estimation for processors featuring modern components. The safety property implies that among all the possible processor states, generated by the binary for all possible inputs, the ones that cause the maximal execution time must be considered. However, complex architectural components, designed to speedup the average case, make it impossible to infer local timing decisions to the global systems as the monotony is broken by the timing anomalies. Therefore, a large number of states must be analysed, generating a combinatorial explosion. Our approach starts with a value analysis of the binary code performed by abstract interpretation. The inherent imprecision of its results is taken into account by the initially concrete abstract state machine processor model. Through the use of an internal oracle, it can dynamically adapt to the lack or imprecision of information by choosing a different hierarchy level for all the impacted components. This kind of execution optimises the granularity of the run based on several strategies. State merging is also used, in order to further counter the state space explosion, in the detriment of precision. The merging is based on identified similar states through the use of equivalence classes. This also offers a leverage on the tradeoff between the precision and scalability of the analysis. Time, different abstraction levels of the processor during the same run and symbolic execution are directly added in the ASM model, as opposed to other approaches. This provides us with the needed architectural adaptability and full control over the main target of the analysis: precise WCET estimation. Taking into account a new processor becomes an engineering task as a new model for the processor is given in our extension of the ASM, with little syntactical differences. This in made possible by the seamless integration of the WCET estimation alongside the ASM semantics, which must not be changed whenever a new platform is considered.
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hal-01214957 , version 1 (13-10-2015)


  • HAL Id : hal-01214957 , version 1


Vladimir-Alexandru Paun, Bruno Monsuez, Philippe Baufreton. Hierarchical Timed Symbolic Abstract State Machines for precise WCET estimation. IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Aug 2013, Taipei, Taiwan. ⟨hal-01214957⟩


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