Hierarchical Timed Abstract State Machines for WCET Estimation
Résumé
In this paper we present an extension of the Abstract State Machines suited for the modelling of complex processors in the context of system verification. Hard real-time systems use evermore complex processors as their certification guidelines are getting tighter and more explicit regarding the verification of software. Besides processor simulation, the goal of our model is to provide a base for worst-case execution time estimation, providing abstraction capabilities that enable the scaling of analysis. The main difference between our model and other ASM extensions is that we define time as a mean to enable time accurate runs and hierarchical abstraction levels of components that can be dynamically chosen during the execution while staying the closest possible to the original ASM mathematical foundation. The model is also designed to choose a suited component definition in order to adapt to information precision on data values. The time extension helps modelling non-instantaneous actions which is essential for real-time systems. Adaptable precision and separation of the analysis from the model of the processor, will proove well suited for integration into a worst-case execution time estimation tool.