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Hierarchical Timed Abstract State Machines for WCET Estimation

Vladimir-Alexandru Paun , Bruno Monsuez , Philippe Baufreton
International Workshop on Verification and Evaluation of Computer and Communication Systems, Nov 2013, Florence, Italy
Conference papers hal-01214973v1

MOCDEX: Multiprocessor on chip multiobjective design space exploration with direct execution

Riad Ben Mouhoub , Omar Hammami
EURASIP Journal on Embedded Systems, 2006, 2006, pp.054074. ⟨10.1155/es/2006/54074⟩
Journal articles hal-00847913v1

A WCET Estimation Workflow Based on the TWSA Model of SystemC Designs

Vladimir-Alexandru Paun , Nesrine Harrath , Bruno Monsuez
The 32nd IEEE Real-Time Systems Symposium, Nov 2011, Vienna, Austria
Conference papers hal-00672884v1

Eager Stack Cache Memory Transfers

Naji Amine , Florian Brandner
Workshop on Worst-Case Execution Time Analysis, Jul 2016, Toulouse, France
Conference papers hal-02287376v1

Studying Optimal Spilling in the Light of SSA

Quentin Colombet , Florian Brandner , Alain Darte
ACM Transactions on Architecture and Code Optimization, 2015, 11-4 (47), pp.26. ⟨10.1145/2685392⟩
Journal articles hal-01099016v1

Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems

Florian Brandner , Aa Tom Vander
Florian Brandner, ENSTA ParisTech; Tom Vander Aa, Target Compiler Technologies,. Workshop on Optimizations for DSP and Embedded Systems, Feb 2014, Orlando, FL, United States. , pp.44, 2014, 978-1-4503-2595-0
Proceedings hal-01108022v1

Towards a Holistic Definition of Model-Based System Engineering: Paradigm, Modeling and Requirements

Hycham Aboutaleb , Bruno Monsuez
INCOSE International Symposium, 2015, 25 (1), pp.1232 - 1244. ⟨10.1002/j.2334-5837.2015.00126.x⟩
Journal articles hal-01774786v1

A Comparative Study of the Precision of Stack Cache Occupancy Analyses

Naji Amine , Florian Brandner
9th Junior Researcher Workshop on Real-Time Computing, Nov 2015, Lille, France. pp.13-16
Conference papers hal-02287276v1

Worst-Case Execution Time Analysis of Predicated Architectures

Florian Brandner , Naji Amine
Workshop on Worst-Case Execution Time Analysis, Jun 2017, Dubrovnik, Croatia. pp.1-13, ⟨10.4230/OASIcs.WCET.2017.6⟩
Conference papers hal-02288493v1

A Comparative Study of the Precision of Stack Cache Occupancy Analyses

Amine Naji , Florian Brandner
9th Junior Researcher Workshop on Real-Time Computing, Julien Forget, Nov 2015, Lille, France. pp.4
Conference papers hal-01246343v1
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Adaptable and Precise Worst Case Execution Time Estimation Tool

Vladimir-Alexandru Paun , Bruno Monsuez
Languages, Compilers, Tools and Theory for Embedded Systems WiP, Jun 2012, Beijing, China
Conference papers hal-01214943v1

Efficient Context Switching for the Stack Cache

Sahar Abbaspour , Florian Brandner , Amine Naji , Mathieu Jan
Proceedings of the 23rd International Conference on Real Time and Networks Systems, Julien Forget (Université de Lille, France), Nov 2015, Lille, France. pp.10, ⟨10.1145/2834848.2834861⟩
Conference papers hal-01246348v1
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Intelligent Drone Swarm for Search and Rescue Operations at Sea

Vincenzo Lomonaco , Angelo Trotta , Marta Ziosi , Juan de Dios Yáñez Ávila , Natalia Díaz-Rodríguez et al.
Workshop on AI for Good, NeurIPS 2018 (Neural Information Processing Systems), Dec 2018, Montreal, Canada
Conference papers hal-01951515v1
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High performance motion detection: some trends toward new embedded architectures for vision systems

Lionel Lacassagne , Antoine Manzanera , Julien Denoulet , Alain Mérigot
Journal of Real-Time Image Processing, 2009, 4 (2), pp.127-146. ⟨10.1007/s11554-008-0096-7⟩
Journal articles hal-01131002v1

A loosely synchronizing asynchronous router for TDM-scheduled NOCs

Ioannis Kotleas , Dean Humphreys , Rasmus Bo Sørensen , Evangelia Kasapaki , Florian Brandner et al.
International Symposium on Networks-on-Chip, Davide Bertozzi; Luca Benini, Sep 2014, Ferrara, Italy. pp.8, ⟨10.1109/NOCS.2014.7008774⟩
Conference papers hal-01108070v1
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Alignment of Memory Transfers of a Time-Predictable Stack Cache

Sahar Abbaspour , Florian Brandner
2014, pp.4
Other publications hal-01108105v1

Quantifying System Complexity in Design Phase Using Higraph-Based Models

Hycham Aboutaleb , Bruno Monsuez
INCOSE International Symposium, 2016, 26 (1), pp.238 - 252. ⟨10.1002/j.2334-5837.2016.00157.x⟩
Journal articles istex hal-01774785v1
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On the Determinism of Multi-core Processors

Vladimir-Alexandru Paun , Bruno Monsuez , Philippe Baufreton
French Singaporean Workshop on Formal Methods and Applications, Jul 2013, Singapour, Singapore. ⟨10.4230/OASIcs.FSFMA.2013.32⟩
Conference papers hal-01214947v1
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Hierarchical Timed Symbolic Abstract State Machines for precise WCET estimation

Vladimir-Alexandru Paun , Bruno Monsuez , Philippe Baufreton
IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, Aug 2013, Taipei, Taiwan
Conference papers hal-01214957v1
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Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis

Sahar Abbaspour , Alexander Jordan , Florian Brandner
14th International Workshop on Worst-Case Execution Time Analysis, Jul 2014, Madrid, Spain. pp.83-92
Conference papers hal-01056216v1

Trade-off in logical radiation hardening: Approach, mechanisms, and reliability impacts

Hycham Aboutaleb , Bruno Monsuez
2016 Annual Reliability and Maintainability Symposium (RAMS), Jan 2016, Tucson, United States. ⟨10.1109/RAMS.2016.7448036⟩
Conference papers hal-01774798v1

Measuring Complexity of System/Software Architecture Using Higraph-Based Model

Hycham Aboutaleb , Bruno Monsuez
International MultiConference of Engineers and Computer Scientists, Mar 2017, Hong Kong, China
Conference papers hal-01774800v1
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Automatic Embedded Multicore Generation and Evaluation Methodology: a Case Study of a NOC Based 2400-cores on Very Large Scale Emulator

Omar Hammami , X. Li , L. Burgun , S. Delerse
WARP - 5th Annual Workshop on Architectural Research Prototyping, Jun 2010, Saint Malo, France
Conference papers inria-00494176v1