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hal-01108022v1  Directions of work or proceedings
Florian BrandnerAa Tom Vander. Proceedings of the 11th Workshop on Optimizations for DSP and Embedded Systems
Florian Brandner, ENSTA ParisTech; Tom Vander Aa, Target Compiler Technologies,. Workshop on Optimizations for DSP and Embedded Systems, Feb 2014, Orlando, FL, United States. pp.44, 2014, 978-1-4503-2595-0
hal-01108053v1  Conference papers
Stefan HeppFlorian Brandner. Splitting functions into single-entry regions
International Conference on Compilers, Architecture and Synthesis for Embedded Systems, Karam S. Chatha (Qualcomm Research); Rolf Ernst (TU Braunschweig), Oct 2014, New Delhi, India. pp.10, ⟨10.1145/2656106.2656128⟩
hal-01774798v1  Conference papers
Hycham AboutalebBruno Monsuez. Trade-off in logical radiation hardening: Approach, mechanisms, and reliability impacts
2016 Annual Reliability and Maintainability Symposium (RAMS), Jan 2016, Tucson, United States. ⟨10.1109/RAMS.2016.7448036⟩
hal-01108070v1  Conference papers
Ioannis KotleasDean HumphreysRasmus SørensenEvangelia KasapakiFlorian Brandner et al.  A loosely synchronizing asynchronous router for TDM-scheduled NOCs
International Symposium on Networks-on-Chip, Davide Bertozzi; Luca Benini, Sep 2014, Ferrara, Italy. pp.8, ⟨10.1109/NOCS.2014.7008774⟩
hal-02287276v1  Conference papers
Naji AmineFlorian Brandner. A Comparative Study of the Precision of Stack Cache Occupancy Analyses
9th Junior Researcher Workshop on Real-Time Computing, Nov 2015, Lille, France. pp.13-16
hal-01108029v1  Journal articles
Florian BrandnerAlexander Jordan. Refinement of worst-case execution time bounds by graph pruning
Computer Languages, Systems and Structures, Elsevier, 2014, 40 (3-4), pp.16. ⟨10.1016/j.cl.2014.09.001⟩
hal-02288493v1  Conference papers
Florian BrandnerNaji Amine. Worst-Case Execution Time Analysis of Predicated Architectures
Workshop on Worst-Case Execution Time Analysis, Jun 2017, Dubrovnik, Croatia. pp.1-13, ⟨10.4230/OASIcs.WCET.2017.6⟩
hal-02287376v1  Conference papers
Naji AmineFlorian Brandner. Eager Stack Cache Memory Transfers
Workshop on Worst-Case Execution Time Analysis, Jul 2016, Toulouse, France